
	#include "arm_a8.h"

#define  EGON2_SRAM_BASE        0
#define  EGON2_SRAM_SIZE        ( 32 * 1024 )
#define  BOOT0_STACK_BOTTOM     ( EGON2_SRAM_BASE + EGON2_SRAM_SIZE )

_start:
	// mrs r0, cpsr
	// bic r0, r0, #ARMV7_MODE_MASK
	// orr r0, r0, #ARMV7_SVC_MODE
	// orr r0, r0, #( ARMV7_IRQ_MASK | ARMV7_FIQ_MASK )    ;// After reset, ARM automaticly disables IRQ and FIQ, and runs in SVC mode.
	// bic r0, r0, #ARMV7_CC_E_BIT                         ;// set little-endian
	// msr cpsr_c, r0

	mrs	r0, cpsr
	and	r1, r0, #0x1f		@ mask mode bits
	teq	r1, #0x1a		@ test for HYP mode
	bicne	r0, r0, #0x1f		@ clear all mode bits
	orrne	r0, r0, #0x13		@ set SVC mode
	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
	msr	cpsr,r0


;// configure memory system : disable MMU,cache and write buffer; set little_endian;
	// mrc p15, 0, r0, c1, c0
	// bic r0, r0, #( ARMV7_C1_M_BIT | ARMV7_C1_C_BIT )  ;// disable MMU, data cache
	// bic r0, r0, #( ARMV7_C1_I_BIT | ARMV7_C1_Z_BIT )  ;// disable instruction cache, disable flow prediction
	// bic r0, r0, #( ARMV7_C1_A_BIT)                    ;// disable align
	// mcr p15, 0, r0, c1, c0

	bl	cpu_init_cp15

;// set SP for C language
	ldr sp, =BOOT0_STACK_BOTTOM

	bl  set_pll
;/**********************************the end of initializing system*********************************/
	bl  Boot0_C_part

 	b .                                 ;// infinite loop


/*************************************************************************
 *
 * cpu_init_cp15
 *
 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
 * CONFIG_SYS_ICACHE_OFF is defined.
 *
 *************************************************************************/
    //;; ENTRY(cpu_init_cp15)
    .globl cpu_init_cp15
    .align		4;
cpu_init_cp15:
 //   mov	r5, lr			@ Store my Caller
	/*
	 * Invalidate L1 I/D
	 */
	mov	r0, #0			@ set up for MCR
	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
	mcr p15, 0, r0, c7, c10, 4	@ DSB
	mcr p15, 0, r0, c7, c5, 4	@ ISB

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
#ifdef SYS_ICACHE_OFF
	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
#else
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
#endif
	mcr	p15, 0, r0, c1, c0, 0
//	mov	pc, r5			@ back to my caller
    mov     pc, lr


//;; ENDPROC(cpu_init_cp15)
	;; .size cpu_init_cp15, .-cpu_init_cp15
